1. Field of the Invention
This invention relates to a circuit routing structure using fewer variable masks, and a method of making that structure.
2. Description of Related Art
One design method used for custom circuitry on silicon chips is the "gate array," an array of digital logic gates whose connections are programmed to form a circuit satisfying the designer's requirements. Gate arrays are generally programmed by varying one or more masks in the masked lithography process that is commonly used to manufacture semiconductor circuits, so as to provide connectors for routing between circuits in the gate array. In a typical process for constructing semiconductor circuits, masks which may be varied include a contact layer, a metal-1 layer, a via layer, and a metal-2 layer.
One problem that has arisen in the art is that each mask which must be varied has a substantial cost, due to the expense of designing and making the mask. Additional masks also increase the length of the fabrication cycle, and reduce the yield of good semiconductor circuits which are produced. It would be advantageous to provide a system in which elements for routing between circuits in a gate array could be constructed while using a reduced number of programmable layers.